1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a source/drain diffusion layer making use of a MOSFET gate structure.
2. Related Background Art
In a conventional MOSFET manufacturing technology, to provide an offset distance between a gate and a soured/drain diffusion layer, there is employed a technology for forming a side wall to the gate and forming the source/drain diffusion layer by implanting ions into the side wall in a self-aligning manner.
The side wall of the gate is used for the purpose of reducing a short channel effect by forming an offset distance in a horizontal direction with respect to the surface of a substrate between the source/drain diffusion layer as an impurity implantation region and a channel region (channel inversion layer) under the gate.
However, when anisotropic etching is carried out to form the side wall of the gate, the substrate is retracted, that is, the substrate is overetched vertically downward with respect to the surface of substrate. The source/drain diffusion layer acting as the impurity diffusion layer and formed on the retracted surface portion of the substrate is spaced apart from the channel inversion layer formed on the not-retracted surface portion of the substrate under the gate by the amount of retraction of the substrate in a vertical direction with respect to the surface of the substrate, so that parasitic resistance is generated.
A larger amount of retraction of the substrate results in a longer distance between the source/drain diffusion layer and the channel inversion layer. Since the path between the source/drain diffusion layer and the channel inversion layer acts as parasitic capacitance when an element operates, an increase of the distance between the source/drain diffusion layer and the channel inversion layer causes a problem of reduction of a transistor drive current.
Accordingly, there is required a method of manufacturing a semiconductor device that can avoid an increase of parasitic capacitance due to separation of source/drain diffusion layer from a channel inversion layer while providing an offset distance between a gate and the source/drain diffusion layer.
Note that countermeasures for improving a MOSFET manufacturing method for forming source/drain diffusion layer by a self-aligning method using a side wall of a gate have been proposed up to now and commonly known. As to these countermeasures, refer to, for example, Japanese Patent Laid-Open Publication No. 11-261062 (261062/1999).
However, the MOSFET manufacturing method disclosed in the above publication exclusively aims to reduce a manufacturing process and does not aim to solve the above problem.